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LXT334
Quad Short-Haul Transceiver with Clock Recovery
Datasheet
The LXT334 is a quad, short-haul, PCM transceiver for 2.048 MHz or 1.544 MHz transmission systems. Its low impedance transmit output drivers provide constant line impedance whether transmitting marks or spaces. The output pulse amplitudes are also constant, stabilized against supply voltage variations. The LXT334 can be configured for balanced 100/120 or unbalanced 75 systems and exceeds the latest ETSI return loss recommendations. An on-chip pulse shaping circuit generates accurate transmit pulses independent of the transmit clock duty cycle. All transmitters and receivers incorporate a power down mode with output tri-stating. The LXT334 features differential receiver architecture with high noise interference margin. It uses peak detection with a variable threshold for reliable recovery of data as low as 500 mV (up to 12 dB of cable attenuation). The fully digital clock recovery system uses a low frequency master clock of 2.048 MHz or 1.544 MHz as its reference. Each receiver incorporates a combination analog/digital Loss Of Signal (LOS) processor that meets the latest ITU G.775 standard. The LXT334 features a driver failure monitoring circuit in parallel to TTIP and TRING that reports driver shorts.
Applications
s
High density line cards using digital backend ASICs
Product Features
s
s s s
s
s
Fully integrated quad, short-haul PCM transceiver for G.703 2.048 Mbps or 1.544 Mbps operation Single rail supply voltage of 5 V (typical) Low power consumption of 410 mW (typical) Programmable G.703 transmit pulse shaping for G.703 75 , 100 and 120 systems High performance line drivers with constant low impedance for 20 dB return loss (typical) exceeds ETSI 300 166 On-chip band gap voltage reference for stabilized, constant output amplitude
s s s s s s s s
s
High-performance receivers recover data with up to 12 dB cable attenuation Low frequency 1.544 or 2.048 MHz reference clock On-chip clock recovery function Programmable unipolar and bipolar PCM interface On-chip AMI and HDB3 encoder/decoder On-chip Driver Failure Monitoring circuit Local and remote loopback testing function Independent Loss of Signal processor for each channel conforms to ITU G.775 recommendation Small-footprint 64-pin QFP
As of January 15, 2001, this document replaces the Level One document LXT334 -- Quad Short-Haul Transceiver with Clock Recovery.
Order Number: 249077-001 January 2001
Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT334 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners.
Datasheet
Quad Short-Haul Transceiver with Clock Recovery -- LXT334
Contents
1.0 2.0 Pin Assignments & Signal Descriptions .......................................................... 6 Functional Description...........................................................................................11
2.1 Receiver ..............................................................................................................11 2.1.1 Loss Of Signal Detector .........................................................................11 2.1.1.1 LOS Detection at 2.048 MHz.....................................................11 2.1.1.2 LOS Detection at 1.544 MHz.....................................................12 2.1.1.3 In-Service Code Violation Monitoring ........................................12 Transmitter ..........................................................................................................12 2.2.1 Line Protection .......................................................................................13 2.2.2 Transmit All Ones Mode.........................................................................13 2.2.3 Pulse Shape ...........................................................................................13 2.2.4 Driver Failure Monitor.............................................................................13
2.2
3.0 4.0 5.0
Application Information.........................................................................................15 Test Specifications ..................................................................................................22 Mechanical Specifications....................................................................................32
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 LXT334 Block Diagram ......................................................................................... 5 LXT334 64 Pin Assignments and Markings .......................................................... 6 50% AMI Pulse Form ..........................................................................................14 E1 Low Power Tx I/F for Coax Cables ................................................................15 E1 Matched Line Tx I/F for Coax Cables for High Return Loss ..........................16 E1 Matched Line Tx I/F for Twisted-Pair Lines for High Return Loss .................17 E1 Low Power Tx I/F for Twisted-Pair Lines .......................................................18 E1 Rx I/F for Coax Cables...................................................................................18 E1 Rx I/F for Twisted-Pair Lines..........................................................................18 T1 Low Power Tx I/F for Twisted-Pair Lines .......................................................18 T1 Matched Line Tx I/F for Twisted-Pair Lines....................................................19 T1 Rx I/F for Twisted-Pair Lines..........................................................................19 E1 120 W and 75 W Matched Line Applications .................................................21 LXT334 Transmit Timing Diagram ......................................................................27 LXT334 Receive Timing Diagram .......................................................................28 2.048 MHz Pulse Mask G.703.............................................................................29 1.544 MHz Pulse Mask, G.703............................................................................29 Jitter Tolerance--G.823 ......................................................................................30 Jitter Attenuation--G.735 ....................................................................................31 Package Specifications .......................................................................................32
Datasheet
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LXT334 -- Quad Short-Haul Transceiver with Clock Recovery
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 LXT334 Pin Descriptions....................................................................................... 7 Operating Mode Summary .................................................................................. 14 Transformer Selection Guide1 ............................................................................ 19 Transmit Transformer and Resistor Combinations ............................................. 20 Absolute Maximum Ratings ................................................................................ 22 Recommended Operating Conditions ................................................................. 22 DC Characteristics (over recommended range).................................................. 22 2.048 MHz Transmit Characteristics in Transformer Coupling Mode (over recommended range)................................................................................. 23 1.544 MHz Transmit Characteristics (over recommended range) ...................... 24 2.048 MHz Receive Characteristics (over recommended range) ....................... 25 1.544 MHz Receive Characteristics (over recommended range) ....................... 26 Transmit Timing Characteristics (over recommended range) ............................. 26 Receive Timing Characteristics (over recommended range) .............................. 27 Relevant Recommendations ............................................................................... 31
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Datasheet
Quad Short-Haul Transceiver with Clock Recovery -- LXT334
Figure 1. LXT334 Block Diagram
Datasheet
5
LXT334 -- Quad Short-Haul Transceiver with Clock Recovery
1.0
Pin Assignments & Signal Descriptions
Figure 2. LXT334 64 Pin Assignments and Markings
Part # LOT # FPO #
LXT334QFP XX XXXXXX XXXXXXXX
Rev #
Package Topside Markings Marking Part # Rev # Lot # FPO # Unique identifier for this product family. Identifies the particular silicon "stepping" -- refer to the specification update for additional stepping information. Identifies the batch. Identifies the Finish Process Order. Definition
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Datasheet
Quad Short-Haul Transceiver with Clock Recovery -- LXT334
Table 1.
Pin # Sym
LXT334 Pin Descriptions
I/O1 Description Master Clock Input. An independent and free-running 2.048 or 1.544 MHz clock input generates the internal reference clocks for all transceivers. On Loss of Signal (LOS), the LXT334 derives RCLKx from this master clock. With MCLK asserted High, the LXT334 disables the PLL clock recovery circuits. The transceiver then feeds RPOSx and RNEGx to an internal XOR gate that performs logically-exclusive ORs for both data signals and connects this output to RCLKx for external clock recovery. In this mode, the LXT334 operates as a data recovery circuit. With MCLK asserted Low, the LXT334 powers down its clock and data recovery circuits and switches the output pins RCLKx, RPOSx and RNEGx to tri-state mode. Driving both MCLK and TCLKx Low powers the device down. MCLK Operating Mode Clocked Data/Clock Recovery L Power Down H Data Recovery Transmit Clock/Transmit Power Down Input-Port 0. All TCLKx pins are identical. The LXT334 samples TPOSx and TNEGx on the falling edge of TCLKx. With TCLKx asserted Low, the total transmit path, including the output drivers, enters a low-power, high-Z mode with all analog and digital circuitry powered down. With TCLKx asserted High for more than 16 clock cycles, the TPOSx and TNEGx duty cycles determine the transmit output pulse widths. In this mode, the LXT334 operates as a line driver. TCLKx Operating Mode Clocked Transmitter H Line Driver (or TAOS if MCLK is Clocked) L Power Down MCLK active with TCLKx High sets TAOS (Transmit All Ones) Mode. Transmit Positive Data/Transmit Data Input-Port 0. All TPOSx/TDATAx pins are identical. In bipolar mode this pin (TPOSx) acts as active High input for the positive pulse to be transmitted. In unipolar mode this pin (TDATAx) acts as active High input for the data to be transmitted on the line. Transmit Negative Data/Unipolar-Bipolar Select Input-Port 0. All TNEGx/UBSx pins are identical. In bipolar mode, this pin acts as input for the negative pulse to be transmitted. If this pin is asserted High for more than 16 TCLK cycles, the LXT334 switches to unipolar mode. The device immediately returns to bipolar mode once this pin goes Low. UBSx Operating Mode L Bipolar Mode H Unipolar Mode Transmit Clock/Transmit Power Down Input-Port 1. See TCLK0, pin 2. Transmit Positive Data/Transmit Data Input-Port 1. See TPOS0/TDATA0, pin 3. Transmit Negative Data/Unipolar-Bipolar Select Input-Port 1. See TNEG0/UBS0, pin 4. Ground. Transmit Tip Output-Port 0. All pin pairs TTIPx/TRINGx are identical. Pin pairs TTIPx/TRINGx are differential line driver outputs designed to drive 75 unbalanced or 100 /120 balanced cables using transformer coupling. Transmit Ground-Port 0. Ground return for transmit driver 0. Transmit Positive Supply-Port 0. +5 VDC power supply input for transmit driver 0. Transmit Ring Output-Port 0. All pin pairs TTIPx/TRINGx are identical. Pin pairs TTIPx/TRINGx are differential line driver outputs designed to drive 75 unbalanced or 100 /120 balanced cables using transformer coupling. See TTIP0, pin 9. Transmit Tip Output-Port 1. See TTIP0, pin 9.
1
MCLK
DI
2
TCLK0
DI
3
TPOS0/ TDATA0
DI
4
TNEG0/ UBS0
DI
5 6 7 8 9 10 11 12 13
TCLK1 TPOS1/ TDATA1 TNEG1/ UBS1 GND TTIP0 TGND0 TVCC0 TRING0 TTIP1
DI DI DI S AO S S AO AO
1. Entries in I/O column are: DI = digital input; DO = digital output; DI/O = digital input/output; AI = analog input; AO = analog output; S = supply. Note: Do not leave digital inputs floating, with the exception of pins 17, 18, and 55-58.
Datasheet
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LXT334 -- Quad Short-Haul Transceiver with Clock Recovery
Table 1.
Pin # 14 15 16 Sym
LXT334 Pin Descriptions (Continued)
I/O1 S S AO Description Transmit Ground-Port 1. Ground return for transmit driver 1. Transmit Positive Supply-Port 1. +5 VDC power supply input for transmit driver 1. Transmit Ring Output-Port 1. See TRING0, pin 12. Mode 1 Select Input. While CNTL1 is Low, and if this pin is asserted Low, all the LXT334 drivers are configured for low power mode with a typical peak pulse output voltage of 3 V. If this pin is asserted High, the LXT334 configures its line drivers for matched line drive mode with a typical peak pulse output voltage of 4 V. Both the driver and the receivers are set to drive transformers. MODE1 Operating Mode L Low Power Mode (See Figure 4 and Figure 7) H Matched Line Drive Mode (See Figure 5 and Figure 6) If CNTL1 is High, MODE1 controls the load-matching circuitry in the transceiver: MODE1 Load H 75 L 120 Mode 2 Select Input. If this pin is pulled Low, all transceivers operate in E1 mode using AMI encoding. With this pin pulled High, all transceivers enter E1 mode using HDB3 encoding if operated in Unipolar Mode. With this pin left open the LXT334 enters T1 mode according to Recommendation G.703. MODE2 Operating Mode L E1 Mode with AMI Encoding H E1 Mode with HDB3 Encoding Open T1 Mode with AMI Encoding Receive Ring Input-Port 0/Receive TIP Input-Port 0. These pins are the inputs of the fully differential line receiver. Loss of Signal Output-Port 0. All LOSx pins are identical. This output is High when the incoming signal has no transitions, i.e., when it is more than 22 dB below the nominal 0 dB level for more than 32 consecutive pulse intervals. The LOS condition is cleared and the output pin returns Low when the incoming signal has transitions (i.e., when the signal level is equal to or greater than 21 dB below the nominal 0 dB level and the average ones density reaches 12.5%.). In data receiver mode, LOSx is a pure analog energy detector. In case of a driver fail condition (DFM = High) this pin acts as a Driver Fail Monitor change of status output to identify the specific driver with the problem.
TGND1 TVCC1 TRING1
17
MODE1
DI
18
MODE2
DI
19 20
RRING0 RTIP0
AI AI
21
LOS0
DO
22 23 24 25 26 27 28 29 30
RRING1R TIP1 LOS1 RRING2R TIP2 LOS2 RRING3R TIP3 LOS3
AI AI DO AI AI DO AI AI DO
Receive Ring Input-Port 1/Receive TIP Input-Port 1. See RRING0, pin 19; RTIP0, pin 20. Loss of Signal Output-Port 1. See LOS0, pin 21. Receive Ring Input-Port 2/Receive TIP Input-Port 2. See RRING0, pin 19; RTIP0, pin 20. Loss of Signal Output-Port 2. See LOS0, pin 21. Receive Ring Input-Port 3/Receive TIP Input-Port 3. See RRING0, pin 19; RTIP0, pin 20. Loss of Signal Output-Port 3. See LOS0, pin 21.
1. Entries in I/O column are: DI = digital input; DO = digital output; DI/O = digital input/output; AI = analog input; AO = analog output; S = supply. Note: Do not leave digital inputs floating, with the exception of pins 17, 18, and 55-58.
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Datasheet
Quad Short-Haul Transceiver with Clock Recovery -- LXT334
Table 1.
Pin # Sym
LXT334 Pin Descriptions (Continued)
I/O1 Description Control 1/Control 2. Settings CNTL1 CNTL2 Result L L RPOS, RNEG valid on falling edge of RCLK L H RPOS, RNEG valid on rising edge of RCLK H L RPOS, RNEG valid on falling edge of RCLK; 120 , 75 load matching selected by MODE1 pin. H H reserved-do not use this setting. Transmit Ring Output-Port 2. See TRING0, pin 12; TTIP0, pin 9. Transmit Power Supply-Port 2. +5 VDC power supply input for transmit driver 2. Transmit Ground-Port 2. Ground return for transmit driver 2. Transmit Tip Output-Port 2. See TTIP0, pin 9. Transmit Ring Output-Port 3. See TRING0, pin 12; TTIP0, pin 9. Transmit Power Supply-Port 3. +5 VDC power supply input for transmit driver 3. Transmit Ground-Port 3. Ground return for transmit driver 3. Transmit Tip Output-Port 3. See TTIP0, pin 9. Positive Supply. Transmit Negative Data/Unipolar-Bipolar Select Input-Port 2. See TNEG0/UBS0, pin 4. Transmit Positive Data/Transmit Data Input-Port 2. See TPOS0/TDATA0, pin 3. Transmit Clock/Transmit Power Down Input-Port 2. See TCLK0, pin 2. Transmit Negative Data/Unipolar-Bipolar Select Input-Port 3. See TNEG0/UBS0, pin 4. Transmit Positive Data/Transmit Data Input-Port 3. See TPOS0/TDATA0, pin 3. Transmit Clock/Transmit Power Down Input-Port 3. See TCLK0, pin 2. Driver Failure Monitor Output. When High, indicates a driver short in one of the output drivers. The LOSx output identifies the specific failing driver in this case. Receive Negative Data/Bipolar Violation Indication Output-Port 3. All RNEGx/BPVx pins are identical. In bipolar mode these pins act as active High bipolar non-return-to-zero (NRZ) receive signal outputs. A High signal on RNEGx corresponds to receipt of a negative pulse on RTIPx/ RRINGx. A High signal on RPOSx corresponds to receipt of a positive pulse on RTIPx/RRINGx. Both signals are valid on the same edge of RCLKx, as determined by CNTL1 and CNTL2. In unipolar mode, the LXT334 asserts the BPVx pin High any time it senses an In-Service Line Code violation. (In data recovery mode, this pin is active Low.) See RPOS3/RDATA3, pin 50; and Functional Description. Receive Positive Data/Receive Data Output-Port 3. A High signal on RPOSx corresponds to receipt of a positive pulse on RTIPx/RRINGx. This signal is valid on the edge of RCLKx determined by CNTL1 and CNTL2.
31 32
CNTL1 CNTL2
DI DI
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
TRING2 TVCC2 TGND2 TTIP2 TRING3 TVCC3 TGND3 TTIP3 VCC TNEG2/ UBS2 TPOS2/ TDATA2 TCLK2 TNEG3/ UBS3 TPOS3/ TDATA3 TCLK3 DFM
AO S S AO AO S S AO S DI DI DI DI DI DI DO
49
RNEG3/ BPV3
DO
50
RPOS3/ RDATA3
DO
In unipolar mode (selected by pulling TNEGx High for more than 16 TCLKx periods) the LXT334 asserts RDATAx High when a mark has been received and is valid on the falling edge of RCLKx. RDATAx is an NRZ receive data output. (In Data Recovery mode, this pin is active Low.) See RNEG3/BPV3, pin 49.
1. Entries in I/O column are: DI = digital input; DO = digital output; DI/O = digital input/output; AI = analog input; AO = analog output; S = supply. Note: Do not leave digital inputs floating, with the exception of pins 17, 18, and 55-58.
Datasheet
9
LXT334 -- Quad Short-Haul Transceiver with Clock Recovery
Table 1.
Pin # Sym
LXT334 Pin Descriptions (Continued)
I/O1 Description Receive Clock Output-Port 3. All RCLKx pins are identical. This pin provides the recovered clock from the signal received at RTIPx and RRINGx. In loss of signal conditions the LXT334 connects MCLK to this pin through internal circuitry. Asserting the MCLK pin High disables the clock recovery circuit and internally connects RPOSx and RNEGx to an XOR that is fed to the RCLKx output for external clock recovery applications.
51
RCLK3
DO
52 53 54
RNEG2/ BPV2 RPOS2/ RDATA2 RCLK2
DO DO DO
Receive Negative Data/Violation Indication Output-Port 2. See RNEG3/BPV3, pin 49; RPOS3/RDATA3, pin 50. Receive Positive Data/Receive Data Output-Port 2. (In Data Recovery Mode, this signal is active Low.) See RPOS3/RDATA3, pin 50; RNEG3/BPV3, pin 49. Receive Clock Output-Port 2. See RCLK3, pin 51. Loopback Mode Select Input-Port 3. All LOOPx pins are identical. Driving this pin Low selects Remote Digital Loopback which causes the LXT334 to ignore any incoming data on TPOSx and TNEGx. It then retransmits data from RTIPx and RRINGx back to TTIPx and TRINGx at the RCLKx rate.
55
LOOP3
DI
Driving this pin High selects Local Loopback which causes the LXT334 to ignore data received on RTIPx and RRINGx and loop data internally from TTIPx and TRINGx back around to the receive inputs. Leaving this pin open selects normal operation mode. LOOP1 Operating Mode L Remote Loopback H Local Loopback Open Normal Operation Mode
56 57 58 59 60 61 62 63 64
LOOP2 LOOP1 LOOP0 RNEG1/ BPV1 RPOS1/ RDATA1 RCLK1 RNEG0/ BPV0 RPOS0/ RDATA0 RCLK0
DI DI DI DO DO DO DO DO DO
Loopback Mode Select Input-Port 2. See LOOP3, pin 55. Loopback Mode Select Input-Port 1. See LOOP3, pin 55. Loopback Mode Select Input-Port 0. See LOOP3, pin 55. Receive Negative Data/Bipolar Violation Indication Output-Port 1. See RNEG3/BPV3, pin 49; RPOS3/RDATA3, pin 50. Receive Positive Data/Receive Data Output-Port 1. (In Data Recovery Mode, this signal is active Low.) See RPOS3/RDATA3, pin 50; RNEG3/BPV3, pin 49. Receive Clock Output-Port 1. See RCLK3, pin 51. Receive Negative Data/Bipolar Violation Indication Output-Port 0. See RNEG3/BPV3, pin 49; RPOS3/RDATA3, pin 50. Receive Positive Data/Receive Data Output-Port 0. (In Data Recovery Mode, this signal is active Low.) See RPOS3/RDATA3, pin 50; RNEG3/BPV3, pin 49. Receive Clock Output-Port 0. See RCLK3, pin 51.
1. Entries in I/O column are: DI = digital input; DO = digital output; DI/O = digital input/output; AI = analog input; AO = analog output; S = supply. Note: Do not leave digital inputs floating, with the exception of pins 17, 18, and 55-58.
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Datasheet
Quad Short-Haul Transceiver with Clock Recovery -- LXT334
2.0
Functional Description
The LXT334 is a fully integrated, quad line interface unit (QLIU) with four complete, independent transceivers. It supports G.703 applications at both 2.048 Mbps and 1.544 Mbps. All transceivers operate at the same frequency, determined by the MCLK input. Refer to the LXT334 block diagram on page 1. The front end of each transceiver interfaces with four lines, one pair for transmit, and one pair for receive. Each transmit/receive line set constitutes a digital data loop for full duplex transmission. Each transceiver also interfaces with back-end processors through bipolar or unipolar data I/O channels, and allows control by hardwired pins for stand-alone operation.
2.1
Receiver
The four receivers in the LXT334 are identical. The following paragraphs describe the operation of a single receiver. The LXT334 receives the input signal at RTIP/RRING via a 1:1 transformer. Data slicers and a peak detector process the received signal. The peak detector samples the received signal and determines its maximum value. A data-rate dependent percentage of peak value goes to the data slicers as a threshold level to ensure an optimum signal-to-noise ratio. The receiver accurately recovers signals with up to -12 dB of cable loss. The minimum receiver sensitivity signal level is approximately 500 mV. Regardless of the received signal level, the LXT334 holds its peak detectors above a minimum level (0.225 V) to provide immunity from impulse noise. After the data slicers process the received signal, it is fed to the data and timing recovery section, and to the receive monitor. The data and timing recovery circuits provide an input jitter tolerance significantly better than required by G.823 as shown in the Test Specifications section. The recovered clock is output at RCLK in both bipolar and unipolar modes. In bipolar mode, recovered data is active High and output at RPOS and RNEG; in unipolar mode recovered data is active High and output at RDATA. If CNTL2 is Low, RPOS and RNEG outputs are valid on the falling edge of RCLK. IF CNTL1 is Low and CNTL2 is High, RPOS and RNEG outputs are valid on the rising edge of RCLK. Asserting MCLK High disables the clock recovery function and switches all receivers to data recovery mode. In data recovery mode the RPOS/RNEG outputs are active Low. Asserting MCLK Low powers all receivers down and holds RPOS/RNEG and RCLK in a high impedance state.
2.1.1
2.1.1.1
Loss Of Signal Detector
LOS Detection at 2.048 MHz
During 2.048 MHz operation, the Loss of Signal (LOS) detector uses a combination analog and digital detection scheme and complies with the ITU G.775 recommendation.
Datasheet
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LXT334 -- Quad Short-Haul Transceiver with Clock Recovery
The receiver monitor loads a digital counter at the RCLK frequency. The monitor increments the counter with each received 0, and resets it to 0 with each received 1 (mark). Any signal ~21 dB below the nominal 0 dB signal for 32 consecutive pulse intervals generates a LOS condition. The LXT334 sets the LOS flag, and replaces the recovered clock with MCLK at the RCLK output in a smooth transition. (Receive operation requires MCLK.) LOS is cleared again when the signal level rises above ~21 dB (typical) below the minimum 0 dB level and the average 1s density reaches 12.5% (4 marks in a 32-bit window). Another smooth transition replaces MCLK with the recovered clock at RCLK. During LOS conditions, received data is output on RPOS/RNEG (or RDATA in unipolar I/O mode). In data recovery mode, the LOS detector uses an analog detection scheme and complies with G.775. During LOS conditions, received data is output on RPOS/RNEG. Any signal 22 dB (typical) below the nominal 0 dB signal for more than approximately 16 s generates a LOS condition. LOS is cleared when the signal level of the first 1 rises to more than 21 dB (typical) below the minimum 0 dB level.
2.1.1.2
LOS Detection at 1.544 MHz
During 1.544 MHz operation, the LXT334 asserts LOS if it receives 175 consecutive zeros, and deasserts LOS when the signal reaches 12.5% ones density (16 marks in a 128-bit window with no more than 99 consecutive zeros).
2.1.1.3
In-Service Code Violation Monitoring
In unipolar AMI I/O Mode, the LXT334 reports bipolar violations using an active High output for one RCLK cycle on the BPV output. A bipolar violation in AMI encoding mode is two consecutive marks of the same polarity. With the HDB3 detector enabled (pulling MODE2 High), the decoder will detect AMI code violations that are not part of a zero substitution code. HDB3 code violations omit sequences of zeros that violate the coding rules. If an HDB3 code violation occurs, the decoder asserts the BPV output for one RCLK cycle during the period of the violating bit. In the event the decoder input receives a sequence of four or more zeros, it asserts the BPV output during the entire sequence of violating data bits.
2.2
Transmitter
The four low-power transmitters in the LXT334 are identical. The following paragraphs describe the operation of a single transmitter. The LXT334 has separate power supply (TVCCx/TGNDx) for each output driver. The LXT334 clocks transmit data from the back end serially into the device at TPOS/TNEG in the bipolar mode, or at TDATA in the unipolar mode. The transmit clock (TCLK) supplies input synchronization. The LXT334 samples the TPOS/ TNEG or TDATA input on the falling edge of TCLK. With no TCLK, the transmitter remains powered down and the TTIP/TRING outputs stay in their high-Z state. Current limiters on the output drivers provide short circuit protection. (Refer to the Test Specifications section.) The LXT334 transmits data as a 50% AMI line code as shown in Figure 3. Pulling TCLK High with no MCLK input bypasses the transmitter PLL. In this case, TPOS and TNEG control the pulse width and polarity on TTIP and TRING.
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Datasheet
Quad Short-Haul Transceiver with Clock Recovery -- LXT334
The line driver provides a constant low output impedance of <3 (typical), regardless of whether it is driving marks or spaces. This well-controlled impedance provides excellent return loss when used with external precision resistors (1% accuracy) in series with the transformer. The Application Information section lists recommended transformer specifications and ratios, and series resistor (Rt) values.
2.2.1
Line Protection
In the receive side, the 1 K series resistors protect the receiver against current surges coupled into the device. Due to the high receiver impedance (40 k typ.) the resistors do not affect the receiver sensitivity. In the transmit side, the Schottky diodes D1-D4 protect the output driver. While not mandatory for normal operation, these protection elements are strongly recommended to improve the design robustness.
2.2.2
Transmit All Ones Mode
Pulling TCLK High for more than 16 MCLK cycles activates Transmit All Ones Mode (TAOS) Mode. In TAOS Mode, the LXT334 ignores the TPOS and TNEG inputs and transmits marks continuously at the MCLK frequency.
2.2.3
Pulse Shape
The LXT334 generates transmit pulse shapes internally using a high-speed PLL and digital-toanalog converters and applies them to the AMI line driver for transmission onto the line at TTIP and TRING.
2.2.4
Driver Failure Monitor
In the event of a short circuit on any transmit line, the Driver Failure Monitor (DFM, common to all transceivers) goes High. The LOS pin (LOSx) for that specific port changes its indication status to flag a driver short condition. DFM is in parallel with TTIP and TRING. The LXT334 uses a capacitor, charged by a measure of the driver output current and discharged by a measure of the maximum allowable current, to detect driver failure. Shorted lines draw excessive current, overcharging the capacitor. When the capacitor charge is outside the nominal charge window, the LXT334 reports a driver short circuit failure. During a long string of spaces, this short-induced overcharge eventually bleeds off, clearing the DFM flag.
Datasheet
13
LXT334 -- Quad Short-Haul Transceiver with Clock Recovery
Figure 3. 50% AMI Pulse Form
TTIP Bit Cell 1 TRING 0 1
Table 2.
MCLK clocked clocked clocked L L L L L L L H H H H H H H H H clocked clocked clocked clocked clocked clocked
Operating Mode Summary
TCLK LOOP Open L H Open L H Open L H X Open L H Open L H Open L H Open L H Open L H Receive Mode Data/Clock Recovery Data/Clock Recovery Data/Clock Recovery Power Down Power Down Power Down Power Down Power Down Power Down Power Down Data Recovery Data Recovery Data Recovery Data Recovery Data Recovery Data Recovery Data Recovery Data Recovery Data Recovery Data/Clock Recovery Data/Clock Recovery Data/Clock Recovery Data/Clock Recovery Data/Clock Recovery Data/Clock Recovery Transmitter Mode Normal Normal Normal Normal Normal Normal Line Driver Line Driver Line Driver Power Down Normal Line Driver Normal Power Down Power Down Power Down Line Driver Line Driver Line Driver Power Down Power Down Power Down Transmit All Ones Normal Transmit All Ones Loop No Loopback Remote Loopback Local Loopback No Loopback No Remote Loopback No Effect on Operation No Loopback No Remote Loopback No Effect on Operation No Loopback No Loopback Remote Loopback Local Loopback No Loopback No Effect on Operation No Local Loopback No Loopback Remote Loopback Local Loopback No Loopback No Effect on Operation No Local Loopback No Loopback Remote Loopback Local Loopback
clocked clocked clocked clocked clocked clocked H H H L clocked clocked clocked L L L H H H L L L H H H
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Datasheet
Quad Short-Haul Transceiver with Clock Recovery -- LXT334
3.0
Application Information
Figure 4. E1 Low Power Tx I/F for Coax Cables
Vcc
TTIP
D1 D2
1.266 : 1
3V
D3
TRING
75
D4
Vcc
D1 - D4 = International Rectifier: 11DQ04 or 10BQ060; Motorola: MBR0540T1
Datasheet
15
LXT334 -- Quad Short-Haul Transceiver with Clock Recovery
Figure 5. E1 Matched Line Tx I/F for Coax Cables for High Return Loss
Vcc
TTIP
D1 D2
26.1
1 : 1.185
4V
TRING
CRT D3 26.1 D4
75
Vcc
CRT: See Test Specifications section of this data sheet D1 - D4 = International Rectifier: 11DQ04 or 10BQ060; Motorola: MBR0540T1
16
Datasheet
Quad Short-Haul Transceiver with Clock Recovery -- LXT334
Figure 6. E1 Matched Line Tx I/F for Twisted-Pair Lines for High Return Loss
Vcc D1 D2 26.1 1 : 1.5
TTIP
4V
D3 TRING D4
CRT 26.1
120
CRT: See Test Specifications section of this data sheet Vcc D1 - D4 = International Rectifier: 11DQ04 or 10BQ060; Motorola: MBR0540T1
Datasheet
17
LXT334 -- Quad Short-Haul Transceiver with Clock Recovery
Figure 7. E1 Low Power Tx I/F for Twisted-Pair Lines
Vcc D1 1:1
TTIP
3V
TRING
D2 D3 D4
120
Vcc D1 - D4 = International Rectifier: 11DQ04 or 10BQ060; Motorola: MBR0540T1
Figure 8. E1 Rx I/F for Coax Cables
RTIP
1k
1:1 Z = 75
75
RRING
1k
Figure 9. E1 Rx I/F for Twisted-Pair Lines
RTIP
1k
1:1 Z = 120
120
RRING
1k
Figure 10. T1 Low Power Tx I/F for Twisted-Pair Lines
Vcc D1 D2 1:1
TTIP
3V
TRING
D3
100
D4 Vcc D1 - D4 = International Rectifier: 11DQ04 or 10BQ060; Motorola: MBR0540T1
18
Datasheet
Quad Short-Haul Transceiver with Clock Recovery -- LXT334
Figure 11. T1 Matched Line Tx I/F for Twisted-Pair Lines
Vcc D1 D2 D3 TRING D4 Vcc CRT: See Test Specifications section of this data sheet D1 - D4 = International Rectifier: 11DQ04 or 10BQ060; Motorola: MBR0540T1 26.1 26.1 1 : 1.5
TTIP
4V
CRT
100
Figure 12. T1 Rx I/F for Twisted-Pair Lines
RTIP
1k
1:1 Z = 100
100
RRING
1k
Table 3.
Transformer Selection Guide1
Transmit Side Receive side (1:1 Ratio) (20 dB Return Loss) Type Quad Dual Dual Dual Dual Dual Single Single Octal Dual Octal Dual Dual
Manufacturer Part Number PE-65586 PE-65766 PE-68789 Pulse Engineering PE-65762 PE-65861 PE-65861 PE-68789 PE-65389 TG27-1505NX HALO TD64-1205D TG29-1205NX 0553-0013 Bel-Fuse 5006-1C 1:2 Transformer Turns Ratio 1:1.36 1:1.266 1:1.5 1:1.36 1:2 1:1 1:1.185 1.266:1 1:1.36 1:1.26 1:2 1:1.36
1. As of the publication date, Intel, has tested the transformers listed in this table. However, part numbers and specifications change without notice. Design engineers should validate components before committing to their use.
Datasheet
19
LXT334 -- Quad Short-Haul Transceiver with Clock Recovery
Table 3.
Transformer Selection Guide1
Transmit Side Receive side (1:1 Ratio) (20 dB Return Loss) Type Single Dual Octal
Manufacturer Part Number Schott Corp Valor ST 5170T 1:1.36 67129300 ST 5078 Transformer Turns Ratio 1:2 1:1.36
1. As of the publication date, Intel, has tested the transformers listed in this table. However, part numbers and specifications change without notice. Design engineers should validate components before committing to their use.
Table 4.
Transformer 1.266:1 1:1 1:1.185 1:1.5 1:1.36 1:1.36 1:2 1:2
Transmit Transformer and Resistor Combinations
Resistor 0 0 26.1 26.1 25 25 15 15 Return Loss1 < 1 dB < 1 dB 20 dB 20 dB 18 dB 18 dB CNTL1 Low Low Low Low Low Low High High MODE1 Low Low High High High High High Low Impedance 75 120 75 120 75 120 75 120
8 dB 8 dB
1. Typical values 51 kHz - 3.078 MHz
20
Datasheet
Quad Short-Haul Transceiver with Clock Recovery -- LXT334
Figure 13. E1 120 and 75 Matched Line Applications
OSCILLATOR 2.048 MHz
+5 V
60 F
1
68 F
68 F
68 F
68 F
1 F 100 nF
TVS1
TVCC3
TVCC2 TGND3
TVCC1 TGND2
TVCC0 TGND1
VCC TGND0
GND
R1
MCLK TCLK0 TPOS0 TNEG0 RPOS0 RNEG0 RCLK0 TCLK1 TPOS1 TNEG1 RPOS1 RNEG1 RCLK1 TCLK2 TPOS2 TNEG2 RPOS2 RNEG2 RCLK2 TCLK3 TPOS3 TNEG3 RPOS3 RNEG3 RCLK3
MCLK TCLK0 TPOS0 TNEG0 RPOS0 RNEG0 RCLK0 TCLK1 TPOS1 TNEG1 RPOS1 RNEG1 RCLK1 TCLK2 TPOS2 TNEG2 RPOS2 RNEG2 RCLK2 TCLK3 TPOS3 TNEG3 RPOS3 RNEG3 RCLK3
TTIP0 TRING0 RTIP0 RRING0 TTIP1 TRING1 RTIP1 RRING1
1:1.36
C1
See INSET for circuitry
R1
R2 R2 R1 See INSET for circuitry
R3
1:1 1:1.36
C1
R1
Quad Framer with Jitter Attenuation
R2 R2
R3
LXT334
1:1
R1 See INSET for circuitry
TTIP2 TRING2 RTIP2 RRING2
1:1.36
C1
INSET
2
VCC D1
R1
R2 R2
R3
TTIPx
R1
TTIP3 TRING3 RTIP3
See INSET for circuitry
1:1 1:1.36
C1
D2
R1
VCC
R2 R2
R3
TRINGx
D3
MODE1 MODE2 CNTL1 CNTL2 LOOP<0:3>
RRING3
VCC
1:1
D4
DFM LOS3 LOS2 LOS1 LOS0
10k 1 Place this capacitor as close as possible to TVCC and TGND pins. Strongly recommended for environments where latch-up is a concern
2
Application Component R1. Transmit resistor R2. Receive resistor R3. Receive terminating resistor C1. Transmit capacitor (typical) D1 - D4. Protection diodes (Schottky) TVS1. Transient Voltage Suppressor 120 25 1 k 120 180 pF International Rectifier: 11DQ04 or 10BQ060 Motorola: MBR0540T1 Semtech: SMCJ5.0AC or equivalent 75 25 1 k 75 180 pF
Datasheet
21
LXT334 -- Quad Short-Haul Transceiver with Clock Recovery
4.0
Note:
Test Specifications
The minimum and maximum values in Table 5 through Table 14 and Figure 14 through Figure 19 represent the performance specifications of the LXT334 and are guaranteed by test except, where noted, by design or other correlation methods. Absolute Maximum Ratings
Parameter Sym RVCC, RGND
1
Table 5.
Min -0.3 GND -0.3 -6 - -10 - - -65 -
Max 6.0 RVCC + 0.3 RVCC + 0.3 100 10 100 20 +150 1
Unit V V V mA mA mA mA C W
DC supply voltage Input voltage on any pin
VIN VIN
2
Input voltage on RTIP/RRING Transient latchup current on any pin Input current on any digital pin3 DC input current on TTIP, TRING
3 3
IIN IIN IIN IIN TSTOR -
DC input current on RTIP, RRING Storage temperature Total package power dissipation
Caution: Exceeding these values may cause permanent damage to the device. Operation is not guaranteed under these conditions. Exposure to absolute maximum rating conditions for extended periods may adversely affect device reliability. 1. Referenced to ground. 2. Exceeding these values will cause SCR latch-up. 3. Constant input current.
Table 6.
Recommended Operating Conditions
Parameter Sym V+ TA Min 4.75 -40 Typ 5.0 25 Max 5.25 +85 Unit V Test Condition
DC supply voltage1 Ambient operating temperature 1. TVcc must not differ from RVCC by more than 0.3 V.
C
Table 7.
DC Characteristics (over recommended range)
Parameter High level input voltage Low level input voltage Sym VIH VIL
2
Min 2.0 -- 3.5 --
Typ1 - - - -
Max - 0.8 - 0.4
Unit V V V V
Test Condition
Digital I/O pins High level output voltage
VOH VOL
IOUT= -400A IOUT= 1.6 mA
Low level output voltage2
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Output Drivers will output CMOS logic levels into CMOS loads. 3. 100% 1s density. Power dissipation including device load while driving a matched line over the operating temperature range. Digital inputs are within 10% of the supply rails and digital outputs are driving a 50 pF load. 4. 50% 1s density. Power dissipation including device load while driving a line without matching resistors over the operating temperature range. Digital inputs are within 10% of the supply rails and digital outputs are driving a 50 pF load. 5. Applies to the following pins: 9, 12, 13, 16, 33, 36, 37, 40, 49-54, 59-64.
22
Datasheet
Quad Short-Haul Transceiver with Clock Recovery -- LXT334
Table 7.
DC Characteristics (over recommended range) (Continued)
Parameter Sym IIL IHZ - - VINL VINH VINM IINL IINH PD PD - PD PD - ICCO Min -10 -10 - - - 3.5 2.3 - - - - - - - - - - - - - 2.5 - - 660 660 680 410 410 370 - Typ1 - Max +10 +10 50 150 1.5 - 2.7 50 50 750 750 895 470 470 500 10 Unit A A mA mA V V V A A mW mW mW mW mW mW mA Figure 5 Figure 6 Figure 11 Figure 4 Figure 7 Figure 10 pins 17, 18, 55, 56, 57, 58 See Figure 5 and Figure 6 See Figure 10 Test Condition
Input leakage current (digital input pins) Tristate leakage current Driver short circuit current E1 T1 Low level input voltage High level input voltage MODE input pins Midrange input voltage Low level input current High level input current 75 system (MODE1=H) Total power dissipation 3 120 system (MODE1=H) 100 system (MODE1=H; MODE2=Open) 75 system (MODE1=L) Total power dissipation4 120 system (MODE1=L) 100 system (MODE1=L; MODE2=Open)
5
Power down current
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Output Drivers will output CMOS logic levels into CMOS loads. 3. 100% 1s density. Power dissipation including device load while driving a matched line over the operating temperature range. Digital inputs are within 10% of the supply rails and digital outputs are driving a 50 pF load. 4. 50% 1s density. Power dissipation including device load while driving a line without matching resistors over the operating temperature range. Digital inputs are within 10% of the supply rails and digital outputs are driving a 50 pF load. 5. Applies to the following pins: 9, 12, 13, 16, 33, 36, 37, 40, 49-54, 59-64.
Table 8.
2.048 MHz Transmit Characteristics in Transformer Coupling Mode (over recommended range)
Parameter Sym - - - - - - - Min 2.13 2.7 -0.237 -0.3 0.95 - - Typ1 2.37 3.0 0 0 - 1 3 Max 2.61 3.3 0.237 0.3 1.05 - - Unit V V V V - % W Test Condition Tested at the line side. Tested at the line side.
Output pulse amplitude Peak voltage of a space
75 120 75 120
Positive to negative pulse imbalance Transmit amplitude variation with supply Driver output impedance4
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Per ITU I.431 recommendation (4.1.2.3.) for a window of 17 consecutive bits. 3. With no jitter at the input used for synchronization or when using an externally supplied jitter free master clock the peak to peak jitter will not exceed the specified value. 4. Guaranteed by design and other correlation methods.
Datasheet
23
LXT334 -- Quad Short-Haul Transceiver with Clock Recovery
Table 8.
2.048 MHz Transmit Characteristics in Transformer Coupling Mode (over recommended range) (Continued)
Parameter Sym
2, 4 3
Min - - - 0.95 20 20 20 -
Typ1 - - - - - - - 180
Max 200 0.04 0.09 1.05 - - - -
Unit mV U.I. U.I. - dB dB dB pF
Test Condition
Difference between pulse sequences Transmit output jitter Output jitter in loopback mode4
- - - - - - - CRT
20 Hz to 100 kHz 20 Hz to 100 kHz
peak to peak peak to peak At the nominal half amplitude. See Application Information, Figure 5 & Figure 6.
Pulse width ratio of the positive and negative pulses 51 kHz to 102 kHz Transmit return loss4 102 kHz to 2.048 MHz 2.048 MHz to 3.072 MHz Transmit load capacitance
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Per ITU I.431 recommendation (4.1.2.3.) for a window of 17 consecutive bits. 3. With no jitter at the input used for synchronization or when using an externally supplied jitter free master clock the peak to peak jitter will not exceed the specified value. 4. Guaranteed by design and other correlation methods.
Table 9.
1.544 MHz Transmit Characteristics (over recommended range)
Parameter Sym - - - - -
4 4
Min 2.4 -0.15 - - - - - - - 12 -29 0.95
Typ1 3.0 0 1 3 - - - - - - - -
Max 3.6 0.15 - - 0.5 0.02 0.025 0.025 0.05 19 - 1.05
Unit V V %
Test Condition ZL = 100 . ZL = 100 .
Output pulse amplitude Peak voltage of a space Transmit amplitude variation with supply Driver output impedance4 Positive to negative pulse imbalance 10 Hz to 8 kHz Transmit output jitter 2
dB U.I U.I. peak to peak U.I. U.I. dB dB -
- - - - - - -
8 kHz to 40 kHz
10 Hz to 40 kHz4 Broad Band
Output power level Output power
772 kHz
3, 4
1544 kHz relative to power at 772 kHz4
Ratio of the pulse widths of the positive and negative pulses at the nominal half amplitude
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. With no jitter at the input used for synchronization or when using an externally supplied jitter free master clock the peak to peak jitter will not exceed the specified value. 3. The signal level is the power level measured in a 3 kHz bandwidth at the point where the signal arrives at the distribution frame for an all 1s pattern transmitted. 4. Guaranteed by design and other correlation methods.
24
Datasheet
Quad Short-Haul Transceiver with Clock Recovery -- LXT334
Table 9.
1.544 MHz Transmit Characteristics (over recommended range) (Continued)
Parameter 51 kHz to 102 kHz Sym - - - CRT Min 18 18 18 - Typ1 - - - 180 Max - - - - Unit dB dB dB pF Test Condition See Applications Information section Figure 11.
Transmit return loss
4
102 kHz to 2.048 MHz 2.048 MHz to 3.072 MHz
Transmit load capacitance
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. With no jitter at the input used for synchronization or when using an externally supplied jitter free master clock the peak to peak jitter will not exceed the specified value. 3. The signal level is the power level measured in a 3 kHz bandwidth at the point where the signal arrives at the distribution frame for an all 1s pattern transmitted. 4. Guaranteed by design and other correlation methods.
Table 10. 2.048 MHz Receive Characteristics (over recommended range)
Parameter Permissible cable attenuation2 Receiver dynamic range Signal to noise interference margin 2, 6 Signal to single tone interference margin Data decision threshold Analog loss of signal threshold Loss of signal threshold hysteresis Consecutive zeros before loss of signal 1.2E-5 Hz to 20 Hz Low limit input jitter tolerance 3 RCLK output jitter4, 6 20 Hz to 2.4 kHz
4 6
Sym - DR S/I S/X SRE - - - - - - - - - -
Min - 0.5 -15 -14 43 - - - 36 1.5 0.2 - - - -
Typ1 - - - - 50 2255 2.5 32 - - - 0.01 10 - 40
Max 12 4.2 - - 57 - - - - - - - - 0 -
Unit dB Vp dB dB % mV dB
Test Condition @1024 kHz
Per G.703, O.151, 6 dB of cable. O.151, 6 dB of cable Relative to peak input voltage.
G.775 recommendation U.I. U.I. U.I. U.I. kHz dB k @1024 kHz RTIP to RRING peak to peak G.735 recommendation See Note 1.
8 kHz to 100 kHz 0 Hz to100 kHz
Clock recovery PLL 3 dB bandwidth PLL peaking
6
Receiver input impedance
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. No errors shall occur when the combined signal attenuated by the maximum specified interconnecting cable loss is applied to the input port. See ITU O.151 recommendation for further details. 3. Sine wave jitter and wander with a peak to peak amplitude that corresponds at least to what is specified in Figure 18 shall not cause either a bit error or loss of frame alignment. As test signal an HDB3-coded digital signal with an electrical characteristic that complies with what is set forth in ITU G.703 shall be used. Test sequence is pseudo-random 215-1. See also ITU O.151. 4. If the LXT334 is configured as data receiver only and if a jitter free signal is applied to RTIP and RRING the added jitter must not exceed the specified value. 5. Equal to 22 dB below the nominal 0 dB level in 120 systems. 6. Guaranteed by design and other correlation methods.
Datasheet
25
LXT334 -- Quad Short-Haul Transceiver with Clock Recovery
Table 10. 2.048 MHz Receive Characteristics (over recommended range) (Continued)
Parameter 51 kHz-102 kHz Receiver Return loss
6
Sym - - -
Min 20 20 20
Typ1 - - -
Max - - -
Unit dB dB dB
Test Condition See Application Information section, Figure 8 & Figure 9.
102-2048 kHz 2048 kHz-3072 kHz
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. No errors shall occur when the combined signal attenuated by the maximum specified interconnecting cable loss is applied to the input port. See ITU O.151 recommendation for further details. 3. Sine wave jitter and wander with a peak to peak amplitude that corresponds at least to what is specified in Figure 18 shall not cause either a bit error or loss of frame alignment. As test signal an HDB3-coded digital signal with an electrical characteristic that complies with what is set forth in ITU G.703 shall be used. Test sequence is pseudo-random 215-1. See also ITU O.151. 4. If the LXT334 is configured as data receiver only and if a jitter free signal is applied to RTIP and RRING the added jitter must not exceed the specified value. 5. Equal to 22 dB below the nominal 0 dB level in 120 systems. 6. Guaranteed by design and other correlation methods.
Table 11. 1.544 MHz Receive Characteristics (over recommended range)
Parameter Permissible cable attenuation Receiver dynamic range Undershoot Data decision threshold Loss of signal threshold Allowable consecutive 0s before LOS Low limit input jitter tolerance 18 kHz to 100 kHz Sym - DR US SRT - - - - - - - - - Min - 0.5 - 63 - - 0.430 - - - 20 20 20 Typ1 - - - 70 0.225 175 - 10 - 40 - - - Max 12 4.2 62 77 - - - - 0 - - - - U.I. kHz dB k dB dB dB See Application Information section, Figure 12. RTIP to RRING @ 772 kHz G.735 recommendation Unit dB Vp % % V Relative to peak input voltage. Test Condition @772 kHz
Clock recovery PLL 3 dB bandwidth PLL peaking
2
Receiver input impedance 51 kHz-102 kHz Input return loss2 102-2048 kHz 2048 kHz-3072 kHz
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Guaranteed by design and other correlation methods.
Table 12. Transmit Timing Characteristics (over recommended range)
Parameter E1 Master clock frequency T1 Master clock tolerance Master clock duty cycle MCLK MCLKt - - - 40 1.544 50 - - - 60 MHz ppm % Sym MCLK Min - Typ1 2.048 Max - Units MHz Test Condition
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
26
Datasheet
Quad Short-Haul Transceiver with Clock Recovery -- LXT334
Table 12. Transmit Timing Characteristics (over recommended range)
Parameter E1 Output pulse width T1 E1 Transmit clock frequency T1 Transmit clock tolerance Transmit clock duty cycle TPOS/TNEG duty cycle TPOS/TNEG to TCLK setup time TCLK to TPOS/TNEG hold time TCLK TCLKt TCLKd TPNd tSUT tHT - - 10 48.4 25 25 1.544 50 - - - - - - 90 51.6 - - MHz ppm % % ns ns Normal Mode Line Driver Mode tPW TCLK 274 - 324 2.048 374 - ns MHz Sym tPW Min 219 Typ1 244 Max 269 Units ns Test Condition
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
Figure 14. LXT334 Transmit Timing Diagram
Table 13. Receive Timing Characteristics (over recommended range)
Parameter Receive clock capture range Receive clock duty cycle
2
Sym - RLCKd E1 T1 tPW tPW tPWL tPWL tPWH tPWH
Min - 40 447 594 203 270 - -
Typ1 80 50 488 648 244 324 244 324
Max - 60 529 702 285 378 - -
Unit ppm % ns ns ns ns ns ns
Test Condition
Receive clock pulse width 2 Receive clock pulse width low time Receive clock pulse width high time
E1 T1 E1 T1
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. RCLK duty cycle will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK duty cycles are for worst case jitter conditions (0.2 U.I. displacement for E1 and 0.4 U.I. for T1 operation). 3. This mode disables clock recovery. 4. If MCLK is High, the PLL clock recovery circuits are disabled. RPOSx and RNEGx are fed to an internal XOR gate that connects this output to RCLKx for external clock recovery.
Datasheet
27
LXT334 -- Quad Short-Haul Transceiver with Clock Recovery
Table 13. Receive Timing Characteristics (over recommended range) (Continued)
Parameter RPOS/RNEG data low time (MCLK=H) 3,4 RPOS/RNEG to RCLK rising setup time RCLK rising to RPOS/RNEG hold time E1 T1 E1 T1 Sym tPWD1 tSUR tSUR tHR tHR - Min 200 50 50 50 50 - Typ1 244 203 270 203 270 5 Max 300 - - - - - Unit ns ns ns ns ns ns MCLK = H Test Condition
Delay time between RPOS/RNEG and RCLK
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. RCLK duty cycle will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK duty cycles are for worst case jitter conditions (0.2 U.I. displacement for E1 and 0.4 U.I. for T1 operation). 3. This mode disables clock recovery. 4. If MCLK is High, the PLL clock recovery circuits are disabled. RPOSx and RNEGx are fed to an internal XOR gate that connects this output to RCLKx for external clock recovery.
Figure 15. LXT334 Receive Timing Diagram
28
Datasheet
Quad Short-Haul Transceiver with Clock Recovery -- LXT334
Figure 16. 2.048 MHz Pulse Mask G.703
Figure 17. 1.544 MHz Pulse Mask, G.703
V
0.7
3.0
0.7
Pulse Amplitude
50 ns
50 ns
1.5
0
0.3 1.2
-3T/8
T = time slot width
-T/4
0 Time
T/8
T/4
3T/8
T/2
Datasheet
29
LXT334 -- Quad Short-Haul Transceiver with Clock Recovery
Figure 18. Jitter Tolerance--G.823
1000 UI
100 UI
Jitter
18 UI @ 1.7 Hz
LXT334 Jitter Tolerance
10 UI
3.0 UI @ 2 kHz
ITU G.823, Mar 1993 (E1)
1 UI
1.5 UI @ 20 Hz 1.5 UI @ 2.4 kHz 0.2 UI @ 18 kHz
0.8 UI 0.4 UI
.1 UI 1 Hz
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
Frequency
30
Datasheet
Quad Short-Haul Transceiver with Clock Recovery -- LXT334
Figure 19. Jitter Attenuation--G.735
0 dB ITU G.735 Jitter Attenuation Requirement
100 Hz: -0.1 dB 10 kHz: -5 dB
-5 dB
-10 dB
-15 dB
LXT334 Jitter Attenuation
-20 dB
-25 dB 40 kHz: -25 dB -30 dB
-35 dB
-40 dB
-45 dB 100 kHz: -45 dB -50 dB 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz
Frequency (Hz)
Table 14. Relevant Recommendations
Recommendation ITU G.703 G.704 G.735 G.736 G.775 G.823 O.151 I.431 Physical/electrical characteristics of hierarchical digital interfaces Functional characteristics of interfaces associated with network nodes Characteristics of Primary PCM multiple equipment operating at 2048 kbit/s and offering digital access at 384 kbit/s and/or synchronous digital access at 64 kbit/s Characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s Loss of signal (LOS) and alarm indication (AIS) defect detection and clearance criteria The control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy Specification of instruments to measure error performance in digital systems ISDN Primary Rate: user network interface layer 1 specification ETSI ETS 300 166 Transmission and Multiplexing (TM); Physical and electrical characteristics of hierarchical digital interfaces for equipment using the 2.048 kbp/s-based plesiochronous or synchronous digital hierarchies Description
Datasheet
31
LXT334 -- Quad Short-Haul Transceiver with Clock Recovery
5.0
Mechanical Specifications
Figure 20. Package Specifications
* Part Number: LXT334QE * 64-pin Quad Flat Pack * Extended Temperature Range -40C - +85C
D D1 D3
for sides with even number of pins
e/
2
E1 E3 E
1
3 L1 A A2 A1 L B 3
Inches Dim Min A A1 A2 b D D1 D3 E E1 E3 e L L1 q3 q 5 0 - 0.000 0.100 0.012 0.695 0.549 Max 0.130 0.010 0.120 0.018 0.715 0.553
Millimeters Min - 0.00 2.55 0.30 17.65 13.95 Max 3.30 0.25 3.05 0.45 18.15 14.05
0.472 REF 0.695 0.549 0.715 0.553
12.00 REF 17.65 13.95 18.15 14.05
0.472 REF 0.031 BSC 0.029 0.041
12.00 REF 0.80 BSC 0.73 1.03
0.077 REF 16 7 5 0
1.95 REF 16 7
1. BSC: Basic Spacing Between Centers
32
Datasheet

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